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74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset
May 1998
74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset
General Description
The LVQ174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops.
Features
n Ideal for low power/low noise 3.3V applications n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed pin-to-pin skew AC performance n Guaranteed incident wave switching into 75
Ordering Code:
Order Number 74LVQ174SC 74LVQ174SJ Package Number M16A M16D Package Description 16-Lead (0.150" Wide) Small Outline Integrated Circuit, SOIC JEDEC 16-Lead Molded Small Outline Package, SOIC EIAJ
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbols Connection Diagram
Pin Assignment for SOIC JEDEC and EIAJ
DS011353-1
IEEE/IEC
DS011353-3
Pin Descriptions
Pin Names D0-D5 CP MR Q0-Q5
DS011353-2
Description Data Inputs Clock Pulse Input Master Reset Input Outputs
(c) 1998 Fairchild Semiconductor Corporation
DS011353
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Functional Description
The LVQ174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input's state is transferred to the corresponding flip-flop's output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The LVQ174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
Truth Table
Inputs MR L H H H CP X
N N
Output D X H L X Q L H L Q
L
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Transition
Logic Diagram
DS011353-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings (Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current -0.5V to +7.0V -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V
Recommended Operating Conditions (Note 2)
Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V VCC @ 3.0V 2.0V to 3.6V 0V to VCC 0V to VCC -40C to +85C
125 mV/ns
50 mA 200 mA -65C to +150C 100 mA
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol Parameter VCC (V) 3.0 3.0 3.0 3.0 VOL Maximum Low Level Output Voltage 3.0 IIN IOLD IOHD ICC VOLP VOLV VIHD VILD Maximum Input Leakage Current Minimum Dynamic (Note 4) Output Current Maximum Quiescent Supply Current Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Maximum High Level Dynamic Input Voltage Maximum Low Level Dynamic Input Voltage
Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75 for commercial temperature range is guaranteed. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND. Note 8: Max number of Data Inputs (n) switching. (n - 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz.
TA = +25C Typ
TA = -40C to +85C Guaranteed Limits
Units
Conditions
VIH VIL VOH
Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage
1.5 1.5 2.99
2.0 0.8 2.9 2.58
2.0 0.8 2.9 2.48 0.1 0.44
V V V V V V A mA mA A V V V V
VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A VIN = VIL or VIH (Note 3) IOH = -12 mA IOUT = 50 A VIN = VIL or VIH (Note 3) IOL = 12 mA VI = VCC, GND VOLD = 0.8V Max (Note 5) VOHD = 2.0V Min (Note 5) VIN = VCC or GND (Notes 6, 7) (Notes 6, 7) (Notes 6, 8) (Notes 6, 8)
3.0
0.002
0.1 0.36
3.6 3.6 3.6 3.6 3.3 3.3 3.3 3.3 0.7 -0.6 1.8 1.6
0.1
1.0
36 -25
4.0 0.8 -0.8 2.0 0.8
40.0
3
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AC Electrical Characteristics
TA = +25C CL = 50 pF Min fmax tPLH tPHL tPHL tOSHL, tOSLH Maximum Clock Frequency Propagation Delay CP to Qn Propagation Delay CP to Qn Propagation Delay MR to Qn Output to Output Skew (Note 9) 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 60 90 2.0 2.0 2.0 2.0 2.5 2.5 Typ 90 100 10.8 9.0 10.2 8.5 10.8 9.0 1.0 1.0 16.2 11.5 15.5 11.0 16.2 11.5 1.5 1.5 Max TA = -40C to +85C CL = 50 pF Min 50 70 1.5 1.5 1.5 1.5 2.0 2.0 18.0 12.5 17.0 12.0 18.0 12.5 1.5 1.5 ns ns ns ns Max MHz
Symbol
Parameter
VCC (V)
Units
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design.
AC Operating Requirements
TA = +25C CL = 50 pF Typ tS tH tW tW trec Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP MR Pulse Width, LOW CP Pulse Width Recovery Time MR to CP 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 2.7 3.3 0.3 3.0 2.5 1.2 1.0 1.2 1.0 1.2 1.0 0 0 8.0 6.5 4.0 3.0 7.0 5.5 7.0 5.5 3.5 2.5 TA = -40C to +85C CL = 50 pF Guaranteed Minimum 10.0 7.0 4.5 3.0 10.0 7.0 10.0 7.0 3.5 2.5 ns ns ns ns ns
Symbol
Parameter
VCC (V)
Units
Capacitance
Symbol CIN CPD (Note 10) Parameter Input Capacitance Power Dissipation Capacitance
Note 10: CPD is measured at 10 MHz.
Typ 4.5 23
Units pF pF
Conditions VCC = Open VCC = 3.3V
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Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead (0.150" Wide) Small Outline Integrated Circuit, SOIC JEDEC Package Number M16A
16-Lead Molded Small Outline Package, SOIC EIAJ Package Number M16D
5
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74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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